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ds07-13746-2e fujitsu semiconductor data sheet copyright?2006-2007 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90360e series mb90362e, mb90362es, mb 90362te, mb90362tes, mb90f362e, mb90f362es, MB90F362TE, MB90F362TEs, mb90367e, mb90367es, mb90367te, mb90367tes, mb90f367e, mb90f367es, mb90f367te, mb90f367tes, mb90v340e-101, mb90v340e-102, mb90v340e-103, mb90v340e-104 description the mb90360e-series, loaded 1 channel full-can* inte rface and flash rom, is general-purpose fujitsu 16-bit microcontroller designing for automotive and indu strial applications. its main feature is the on-board can interfaces, which conform to ver 2.0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a nor mal full-can approach. with the new 0.35 m cmos technology, fujitsu now offers on-chip flash rom program memory up to 64 kbytes. the power supply (3 v) is supplied to the mcu core from an internal regulator circuit. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an inte rnal 42 ns instruction execution time from an external 4 mhz clock. also, main and sub clock can be monito red independently using the clock supervisor function. the unit features a 4-channel input capture unit 1 ch annel 16-bit free running timer, 2-channel uart, and 16- channel 8/10-bit a/d converter as the peripheral resource. * : controller area network (can) - license of robert bosch gmbh note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller.
mb90360e series 2 features ? clock built-in pll clock frequency multiplication circuit selection of machine clocks (pll clocks) is allo wed among frequency division by 2 on oscillation clock and multiplication of 1 to 6 times of oscillation cloc k (for 4 mhz oscillation clock, 4 mhz to 24 mhz) operation by sub clock : internal operating clock fre quency: up to 50 khz (for operating with 100 khz oscillation clock divided two and devices wit hout s-suffix only) is available minimum execution time of instruction : 42 ns (when op erating with 4-mhz oscillation clock and 6-time multiplied pll clock) ? clock supervisor (mb90x367x only) main clock or sub clock is monitored independently internal cr oscillation clock (100 khz typical) can be used as sub clock ? instruction system best suited to controller 16 mbytes cpu memory space 24-bit internal addressing wide choice of data types (bit, byte, word, and long word) wide choice of addres sing modes (23 types) enhanced multiply-divide instructions with sign and reti instructions enhanced high-precision computing with 32-bit accumulator ? instruction system compatible with high- level language (c language) and multitask employing system stack pointer enhanced various pointer indirect instructions barrel shift instructions ? increased processing speed 4-byte instruction queue ? powerful interrupt function powerful 8-level, 34-condition interrupt feature up to 8 channels external interrupts are supported ? automatic data transfer fu nction independent of cpu expanded intelligent i/o service function (ei 2 os) : up to 16 channels ? low power consumption (standby) mode sleep mode (a mode that halts cpu operating clock) main timer mode (timebase timer mode that is transferred from main clock mode) pll timer mode (timebase timer mode that is transferred from pll clock mode) watch mode (a mode that operates sub clock and watch timer only, devices without s-suffix) stop mode (a mode that stops o scillation clock and sub clock) cpu blocking operation mode ? process cmos technology ? i/o port general purpose input/output port (cmos output) : - 34 ports (devices without s-suffix) - 36 ports (devices with s-suffix) ? sub clock pin (x0a and x1a) provided (used for external oscillation), devices without s-suffix not provided (used with internal cr oscillati on in sub clock mode) , devices with s-suffix (continued)
mb90360e series 3 (continued) ? timer timebase timer, watch timer (device wit hout s-suffix) , watchdog timer : 1 channel 8/16-bit ppg timer : 8-bit 2 channels or 16-bit 1 channel 16-bit reload timer : 2 channels 16- bit input/output timer - 16-bit free-run timer : 1 channel (frt0 : icu 0/1/2/3) - 16- bit input capture : (icu) : 4 channels ? full-can interface : up to 1 channel compliant with can specificat ions version 2.0 part a and b 16 message buffers are built in can wake-up function ? uart (lin/sci) : up to 2 channels equipped with full-duplex double buffer clock-asynchronous or clock-synchronous serial transmission is available ? dtp/external interrupt : up to 8 ch annels, can wakeup : up to 1 channel module for activation of expanded intelligent i/o service (ei 2 os) and generation of external interrupt by external input ? delay interrupt generator module generates interrupt request for task switching ? 8/10-bit a/d converter : 16 channels resolution is selectable between 8-bit and 10-bit activation by external trigger input is allowed conversion time : 3 s (at 24-mhz machine clock, including sampling time) ? program patch function address matching detection for 6 address pointers ? low voltage/cpu operation detection reset (devices with t-suffix) detects low voltage (4.0 v 0.3 v) and resets automatically resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 mhz) ? capable of changing input voltage for port automotive/cmos-schmitt input level (initial level is automotive in single-chip mode) ? flash memory security function protects the content of flash me mory (mb90f362x, mb90f367x only)
mb90360e series 4 product lineup * : it is setting of jumper switch (tool vcc) when emul ator (mb2147-01) is used. please refer to the emulator hardware manual for the details. features mb90362e mb90362te mb90362es mb90362tes mb90v340e- 101 mb90v340e- 102 type mask rom product evaluation product cpu f 2 mc-16lx cpu system clock pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz oscillation clock, pll 6) sub clock pin (x0a, x1a) yes no no yes clock supervisor no rom mask rom, 64 kbytes external ram capacitance 3 kbytes 30 kbytes can interface 1 channel 3 channels low voltage/cpu operation detection reset no yes no yes no package lqfp-48p pga-299c emulator-specific power supply * ? yes corresponding evaluation product mb90v340e-102 mb90v340e-101 ? features mb90f362e MB90F362TE mb90f362es MB90F362TEs type flash memory product cpu f 2 mc-16lx cpu system clock pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz oscillation clock, pll 6) sub clock pin (x0a, x1a) yes no clock supervisor no rom flash memory, 64 kbytes ram capacitance 3 kbytes can interface 1 channel low voltage/cpu opera- tion detection reset no yes no yes package lqfp-48p corresponding evaluation product mb90v340e-102 mb90v340e-101
mb90360e series 5 * : it is setting of jumper switch (tool vcc) when emul ator (mb2147-01) is used. please refer to the emulator hardware manual for the details. features mb90367e mb90367te mb90367es mb90367tes mb90v340e- 103 mb90v340e- 104 type mask rom product evaluation product cpu f 2 mc-16lx cpu system clock pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz oscillation clock, pll 6) sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) yes clock supervisor yes rom mask rom, 64 kbytes external ram capacitance 3 kbytes 30 kbytes can interface 1 channel 3 channels low voltage/cpu operation detection reset no yes no yes no package lqfp-48p pga-299c emulator-specific power supply * ? yes corresponding eva product mb90v340e-104 mb90v340e-103 ? features mb90f367e mb90f367t e mb90f367es mb90f367tes type flash memory product cpu f 2 mc-16lx cpu system clock pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz oscillation clock, pll 6) sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) clock supervisor yes rom flash memory, 64 kbytes ram capacitance 3 kbytes can interface 1 channel low voltage/cpu opera- tion detection reset no yes no yes package lqfp-48p corresponding eva product mb90v340e-104 mb90v340e-103
mb90360e series 6 pin assignment ? mb90f362e/te/es/tes, mb90362e/te/es/tes, mb90f367e/te/es/tes, mb90367e/te/es/tes (top view) (fpt-48p-m26) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 34 36 48 47 46 45 44 43 42 41 40 39 38 37 p66/an6/ppgc(d) avss rst vcc vss c x0a/p40 * 1 x1a/p41 * 1 p82/sin0/int14r/tin2 p50/an8 avcc p44/frck0 p80/adtg/int12r p51/an9 x0 x1 p67/an7/ppge(f) avr p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p27/in3 p26/in2 p25/in1 p24/in0 p23/ppgf(e) * 2 p22/ppgd(c) * 2 p21 * 2 p20 * 2 md2 md1 md0 p52/an10 p53/an11/tin3 p54/an12/tot3/int8 p55/an13/int10 p56/an14/int11 p57/an15/int13 p84/sck0/int15r p83/sot0/tot2 p42/rx1/int9r p43/tx1 p86/sot1 p87/sck1 p85/sin1 *1 : mb90f362e/te, mb90362e/te, mb90 f367e/te, mb90367e/te : x0a, x1a mb90f362es/tes, mb90362es/tes, mb90f 367es/tes, mb90367es/tes : p40, p41 *2 : high current output port
mb90360e series 7 pin description (continued) pin no. pin name i/o circuit type* function 1av cc iv cc power input pin for analog circuit. 2 avr ? power (vref + ) input pin for a/d converter. it should be below v cc . 3 to 8 p60 to p65 h general-purpose i/o port. an0 to an5 analog input pins for a/d converter. 9, 10 p66, p67 h general-purpose i/o port. an6, an7 analog input pins for a/d converter. ppgc (d) , ppge (f) output pins for ppg. 11 p80 f general-purpose i/o port. adtg trigger input pin for a/d converter. int12r external interrupt request input pin for int12. 12 to 14 p50 to p52 h general-purpose i/o port (p50 has different i/o circuit type from mb90v340e) . an8 to an10 analog input pins for a/d converter. 15 p53 h general-purpose i/o port. an11 analog input pin for a/d converter. tin3 event input pin for reload timer 3. 16 p54 h general-purpose i/o port. an12 analog input pin for a/d converter. tot3 output pin for reload timer 3 int8 external interrupt request input pin for int8. 17 to 19 p55 to p57 h general-purpose i/o port. an13 to an15 analog input pins for a/d converter. int10, int11, int13 external interrupt request input pins for int10, int11, int13. 20 md2 d input pin for operation mode specification. 21, 22 md1, md0 c input pins for operation mode specification. 23 rst e reset input pin. 24 v cc ? power input pin (3.5 v to 5.5 v) . 25 v ss ? power input pin (0 v) . 26 c i power supply stabilization capacitor pin. it should be connected to a higher than or equal to 0.1 f ceramic condenser.
mb90360e series 8 (continued) pin no. pin name i/o circuit type* function 27 x0 a oscillation input pin. 28 x1 oscillation output pin. 29 to 32 p27 to p24 g general-purpose i/o port. the register can be set to se lect whether to use a pull-up resistor. this function is enabled in single-chip mode. in3 to in0 event input pins for input capture 0 to 3. 33, 34 p23, p22 j general-purpose i/o port. the register can be set to se lect whether to use a pull-up resistor. this function is enabled in single-chip mode. high current output port. ppgf (e) , ppgd (c) output pins for ppg. 35, 36 p21, p20 j general-purpose i/o port. the register can be set to se lect whether to use a pull-up resistor. this function is enabled in single-chip mode. high current output port. 37 p85 k general-purpose i/o port. sin1 serial data input pin for uart1. 38 p87 f general-purpose i/o port. sck1 clock i/o pin for uart1. 39 p86 f general-purpose i/o port. sot1 serial data output pin for uart1. 40 p43 f general-purpose i/o port. tx1 tx output pin for can1 interface. 41 p42 f general-purpose i/o port. rx1 rx input pin for can1 interface. int9r external interrupt request input pin for int9 (sub) . 42 p83 f general-purpose i/o port. sot0 serial data output pin for uart0. tot2 output pin for reload timer 2. 43 p84 f general-purpose i/o port. sck0 clock i/o pin for uart0. int15r external interrupt request input pin for int15.
mb90360e series 9 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 44 p82 k general-purpose i/o port. sin0 serial data input pin for uart0. int14r external interrupt request input pin for int14. tin2 event input pin for reload timer 2. 45 p44 f general-purpose i/o port (different i/o circuit type from mb90v340e) . frck0 free-run timer 0 clock pin. 46, 47 p40, p41 f general-purpose i/o port (devices with s-suffix and mb90v340e-101/103 only) . x0a, x1a b oscillation pins for sub clock (devices without s-suffix and mb90v340e-102/104 only) . 48 av ss iv ss power input pin for analog circuit.
mb90360e series 10 i/o circuit type (continued) type circuit remarks a oscillation circuit : high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit : low-speed oscillation feedback resistor = approx. 10 m ? c mask rom product : cmos hysteresis input pin flash memory product : cmos input pin d mask rom product : cmos hysteresis input pin flash memory product : - cmos input pin - no pull-down e cmos hysteresis input pin x1 x0 standby control signal xout standby control signal x1a x0a xout r cmo s hy s tere s i s inp u t s r pull-down resistor cmos hysteresis inputs r pull-up resistor cmos hysteresis inputs
mb90360e series 11 (continued) type circuit remarks f cmos level output cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) g cmos level output cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) h cmos level output cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) a/d analog input pout nout r cmos hysteresis inputs automotive inputs standby control for input shutdown p-ch n-ch r pull-up control pull-up resistor cmos hysteresis inputs automotive inputs pout nout standby control for input shutdown p-ch n-ch p-ch pout nout r cmos hysteresis inputs analog input automotive inputs standby control for input shutdown p-ch n-ch
mb90360e series 12 (continued) type circuit remarks i protection circuit for power supply input j cmos level output cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) k cmos level output cmos input (with standby-time input shutdown function) automotive input (with standby-time in- put shutdown function) p-ch n-ch pout high current output nout high current output r pull-up control pull-up resistor cmos hysteresis inputs automotive inputs standby control for input shutdown p-ch n-ch p-ch po u t no u t r cmo s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown p-ch n-ch
mb90360e series 13 handling devices 1. preventing latch-up cmos ic chips may suffer latch- up under the following conditions : a voltage higher than v cc pin or lower than v ss pin is applied to an input or output pin. a voltage higher than the rate d voltage is applied between v cc pin and v ss pin. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. use meticulous care not to exceed the rating. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avr) exceed the digital power-supply voltage. 2. treatment of unused pins leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. therefore, they must be pulled up or pulled down through resistors. in this case, those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output st ate and can be left open, or the input state with the above described connection. 3. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 4. precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillato r, use pull-down handling on the x0a pin and leave the x1a pin open. 5. notes on during operation of pll clock mode on this microcontroller, if in case t he crystal oscillator breaks off or an ex ternal reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guarant ee results of operations if such failure occurs. 6. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent malfunction such as latch-up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the curr ent supply source at a low impedance. mb90360e series x0 x1 open
mb90360e series 14 as a measure against power supply noi se, connect a capacitor of about 0.1 f as a bypass capacitor between v cc pin and v ss pin in the vicinity of v cc and v ss pins of the device. 7. pull-up/down resistors the mb90360e series does not support internal pull-up/down resistors (port 2 : built-in pull-up resistors) . use external components where needed. 8. crystal oscillator circuit noises around x0 or x1 pin may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, cr ystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscilla tion circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board artwork surrounding x0 and x1 pins with a ground area for stabilizing the operation. please ask the crystal ma ker to evaluate the oscillational characteristics of the crystal and this device. 9. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc and avr) and analog inpu ts (an0 to an15) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d conv erter power supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc . v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90 3 60e s erie s
mb90360e series 15 10. connection of unused pins of a/d converter if a/d converter is not used connect unused pins of a/d converter to av cc = v cc , av ss = avr = v ss . 11. notes on energization to prevent the internal regulator ci rcuit from malfunctioning, set the vo ltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . 12. stabilization of power supply voltage a sudden change in the power supply voltage may cause the device to malfunction even within the specified v cc power supply voltage operating guarantee range. therefore, the v cc power supply voltage should be stabilized. for reference, the power supply volt age should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz/60 hz) fall below 10 % of the standard v cc power supply voltage and the coefficient of transient fluctuation does not ex ceed 0.1 v/ms at instantaneous power switching. 13. initialization in the device, there are internal registers which are initializ ed only by a power-on reset. to initialize these registers, turn on the power again. 14. notes on using can function to use can function, please set ?1? to direct bit of can direct mode register (cdmr) . if direct bit is set to ?0? (initial value) , wait states will be performed when accessing can registers. note : please refer to hardware manual of ?mb9036 0e series for detail of can direct mode register?. 15. flash security function the security bit is located in the area of the flash memory. if protection code 01 h is written in the security bit, the flash me mory is in the protected state by security. therefore, please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security bit. 16. correspondence with t a = + 105 c or more if used exceeding t a = + 105 c, please consult with us due to the restricted reliability. it is ensured to write/erase da ta to the flash memory between t a = ? 40 c and + 105 c. flash memory size address for security bit mb90f362e mb90f362es MB90F362TE MB90F362TEs mb90f367e mb90f367es mb90f367te mb90f367tes embedded 512 kbits flash memory ff0001 h
mb90360e series 16 block diagrams ? mb90v340e-101/102 ram 30 kbytes uart 5 channels dma sot4 to sot0 sck4 to sck0 sin4 to sin0 av cc av ss avrh avrl adtg da01, da00 ppgf to ppg0 sda1, sda0 scl1, scl0 frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin3 to tin0 tot3 to tot0 ad15 to ad00 a23 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 (int15r to int8r) int7 to int0 ckot an23 to an0 clock controller f 2 mc-16lx core 16-bit i/o timer 0 16-bit free-run timer 1 input capture 8 channels output compare 8 channels can controller 3 channels 16-bit reload timer 4 channels external bus dtp/ external interrupt clock monitor prescaler (5 channels) 8/10-bit a/d converter 24 channels 10-bit d/a converter 2 channels internal data bus 8/16-bit ppg 16 channels i 2 c interface 2 channels x0, x1 x0a, x1a ? rst * : only for mb90v 3 40e-102
mb90360e series 17 ? mb90v340e-103/104 x0, x1 x0a, x1a * rst ram 30 kbytes uart 5 channels dma sot4 to sot0 sck4 to sck0 sin4 to sin0 av cc av ss avrh avrl adtg da01, da00 ppgf to ppg0 sda1, sda0 scl1, scl0 frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin3 to tin0 tot3 to tot0 ad15 to ad00 a23 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 (int15r to int8r) int7 to int0 ckot an23 to an0 clock controller/ monitor cr oscillator circuit 16-bit i/o timer 0 16-bit free-run timer 1 input capture 8 channels output compare 8 channels can controller 3 channels 16-bit reload timer 4 channels external bus dtp/ external interrupt clock monitor prescaler (5 channels) 8/10-bit a/d converter 24 channels 10-bit d/a converter 2 channels internal data bus 8/16-bit ppg 16 channels i 2 c interface 2 channels f 2 mc-16lx core * : only for mb90v 3 40e-104
mb90360e series 1 8 ? mb90f362e/te/es/tes, mb90362e/te/es/tes *1 : only for device s witho u t s - su ffix *2 : only for device s with t- su ffix ram 3 kbytes rom 64 kbytes uart 2 channels 8/16-bit ppg 2 channels sot0, sot1 sck0, sck1 sin0, sin1 ppgf(e), ppgd(c), ppgc(d), ppge(f) in0 to in3 frck0 rx1 tx1 tin2, tin3 tot2, tot3 int8, int9r int10, int11 int12r, int13 int14r, int15r av cc av ss an15 to an0 avr adtg clock controller 16-bit free-run timer 0 input capture 4 channels can controller 1 channel 16-bit reload timer 2 channels dtp/ external interrupt prescaler (2 channels) 8/10-bit a/d converter 16 channels f 2 mc-16lx core internal data bus low voltage/cpu operation detection * 2 x0, x1 x0a, x1a ? 1 rst
mb90360e series 19 ? mb90f367e/te/es/tes, mb90367e/te/es/tes *1 : only for device s witho u t s - su ffix *2 : only for device s with t- su ffix ram 3 kbytes rom 64 kbytes uart 2 channels 8/16-bit ppg 2 channels sot0, sot1 sck0, sck1 sin0, sin1 ppgf(e), ppgd(c), ppgc(d), ppge(f) in0 to in3 frck0 rx1 tx1 tin2, tin3 tot2, tot3 int8, int9r int10, int11 int12r, int13 int14r, int15r av cc av ss an15 to an0 avr adtg x0, x1 x0a, x1a * 1 rst clock controller/ monitor cr oscillator circuit 16-bit free-run timer 0 input capture 4 channels can controller 1 channel 16-bit reload timer 2 channels dtp/ external interrupt prescaler (2 channels) 8/10-bit a/d converter 16 channels f 2 mc-16lx core internal data bus low voltage/cpu operation detection * 2
mb90360e series 20 memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are t he same, the table in rom can be referred without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h practically accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, and its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h 0000ef h 000000 h f90000 h f 8 ffff h f 8 0000 h 00ffff h 007fff h 007900 h 007 8 ff h 000100 h 00 8 000 h mb90 v 340e-101/102 mb90 v 340e-103/104 ffffff h ff0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 000cff h 000100 h 00 8 000 h mb90f362e/te/es/tes mb90362e/te/es/tes mb90f367e/te/es/tes mb90367e/te/es/tes ram 30 k b ytes ram 3 k b ytes 010000 h feffff h 0000f0 h 0000ff h rom (ff b ank) rom (fe b ank) rom (fd b ank) rom (fc b ank) rom (fb b ank) rom (fa b ank) rom (f9 b ank) rom (f 8 b ank) external access area external access area rom (image of ff b ank) peripheral peripheral rom (ff b ank) rom (image of ff b ank) peripheral peripheral : n o access
mb90360e series 21 i/o map (continued) address register abbrevia- tion access resource name initial value 000000 h , 000001 h reserved 000002 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 000003 h reserved 000004 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 000005 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 000006 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 000007 h reserved 000008 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 000009 h , 00000a h reserved 00000b h port 5 analog input enable register ader5 r/w port 5, a/d 11111111 b 00000c h port 6 analog input enable register ader6 r/w port 6, a/d 11111111 b 00000d h reserved 00000e h input level select register ilsr0 r/w ports xxxx0xxx b 00000f h input level select register ilsr1 r/w ports xxxxxxxx b 000010 h , 000011 h reserved 000012 h port 2 direction register ddr2 r/w port 2 00000000 b 000013 h reserved 000014 h port 4 direction register ddr4 r/w port 4 xxx00000 b 000015 h port 5 direction register ddr5 r/w port 5 00000000 b 000016 h port 6 direction register ddr6 r/w port 6 00000000 b 000017 h reserved 000018 h port 8 direction register ddr8 r/w port 8 000000x0 b 000019 h reserved 00001a h port a direction register ddra w port a xxx00xxx b 00001b h to 00001d h reserved 00001e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 00001f h reserved
mb90360e series 22 (continued) address register abbrevia- tion access resource name initial value 000020 h serial mode register 0 smr0 w, r/w uart0 00000000 b 000021 h serial control register 0 scr0 w, r/w 00000000 b 000022 h reception/transmission data register 0 rdr0/ tdr0 r/w 00000000 b 000023 h serial status register 0 ssr0 r, r/w 00001000 b 000024 h extended communication control register 0 eccr0 r, w, r/w 000000xx b 000025 h extended status/control r egister 0 escr0 r/w 00000100 b 000026 h baud rate generator register 00 bgr00 r/w, r 00000000 b 000027 h baud rate generator register 01 bgr01 r/w, r 00000000 b 000028 h serial mode register 1 smr1 w, r/w uart1 00000000 b 000029 h serial control register 1 scr1 w, r/w 00000000 b 00002a h reception/transmission data register 1 rdr1/ tdr1 r/w 00000000 b 00002b h serial status register 1 ssr1 r, r/w 00001000 b 00002c h extended communication control register 1 eccr1 r, w, r/w 000000xx b 00002d h extended status/control r egister 1 escr1 r/w 00000100 b 00002e h baud rate generator register 10 bgr10 r/w, r 00000000 b 00002f h baud rate generator register 11 bgr11 r/w, r 00000000 b 000030 h to 00003a h reserved 00003b h address detect control register 1 pacsr1 r/w address match detection 1 00000000 b 00003c h to 000047 h reserved 000048 h ppg c operation mode control register ppgcc w, r/w 16-bit ppg c/d 0x000xx1 b 000049 h ppg d operation mode control register ppgcd w, r/w 0x000001 b 00004a h ppg c/ppg d count clock select register ppgcd r/w 000000x0 b 00004b h reserved 00004c h ppg e operation mode cont rol register ppgce w, r/w 16-bit ppg e/f 0x000xx1 b 00004d h ppg f operation mode control register ppgcf w, r/w 0x000001 b 00004e h ppg e/ppg f count clock select register ppgef r/w 000000x0 b 00004f h reserved
mb90360e series 23 (continued) address register abbrevia- tion access resource name initial value 000050 h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 b 000051 h input capture edge 0/1 ice01 r/w, r xxx0x0xx b 000052 h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 b 000053 h input capture edge 2/3 ice23 r xxxxxxxx b 000054 h to 000063 h reserved 000064 h timer control status 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 000065 h timer control status 2 tmcsr2 r/w xxxx0000 b 000066 h timer control status 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 000067 h timer control status 3 tmcsr3 r/w xxxx0000 b 000068 h a/d control status 0 adcs0 r/w a/d converter 000xxxx0 b 000069 h a/d control status 1 adcs1 r/w, w 0000000x b 00006a h a/d data 0 adcr0 r 00000000 b 00006b h a/d data 1 adcr1 r xxxxxx00 b 00006c h adc setting 0 adsr0 r/w 00000000 b 00006d h adc setting 1 adsr1 r/w 00000000 b 00006e h low voltage/cpu o peration detection reset control register lvrc r/w, w low voltage/cpu operation detection reset 00111000 b 00006f h rom mirror function select romm w rom mirror xxxxxxx1 b 000070 h to 00007f h reserved 000080 h to 00008f h reserved for can interface 1. refer to ? can controllers? 000090 h to 00009d h reserved 00009e h address detect control register 0 pacsr0 r/w address match detection 0 00000000 b 00009f h delayed interrupt/release register dirr r/w delayed interrupt generation module xxxxxxx0 b 0000a0 h low-power consumption mode control register lpmcr w, r/w low-power consumption control circuit 00011000 b 0000a1 h clock selection register ckscr r, r/w low-power consumption control circuit 11111100 b
mb90360e series 24 (continued) address register abbrevia- tion access resource name initial value 0000a2 h to 0000a7 h reserved 0000a8 h watchdog control register wdtc r, w watchdog timer xxxxx111 b 0000a9 h timebase timer control register tbtc w, r/w timebase timer 1xx00100 b 0000aa h watch timer control register wtc r, r/w watch timer 1x001000 b 0000ab h to 0000ad h reserved 0000ae h flash control status (flash devices only. otherwise reserved) fmcs r, r/w flash memory 000x0000 b 0000af h reserved 0000b0 h interrupt control register 00 icr00 w, r/w interrupt control 00000111 b 0000b1 h interrupt control register 01 icr01 w, r/w 00000111 b 0000b2 h interrupt control register 02 icr02 w, r/w 00000111 b 0000b3 h interrupt control register 03 icr03 w, r/w 00000111 b 0000b4 h interrupt control register 04 icr04 w, r/w 00000111 b 0000b5 h interrupt control register 05 icr05 w, r/w 00000111 b 0000b6 h interrupt control register 06 icr06 w, r/w 00000111 b 0000b7 h interrupt control register 07 icr07 w, r/w 00000111 b 0000b8 h interrupt control register 08 icr08 w, r/w 00000111 b 0000b9 h interrupt control register 09 icr09 w, r/w 00000111 b 0000ba h interrupt control register 10 icr10 w, r/w 00000111 b 0000bb h interrupt control register 11 icr11 w, r/w 00000111 b 0000bc h interrupt control register 12 icr12 w, r/w 00000111 b 0000bd h interrupt control register 13 icr13 w, r/w 00000111 b 0000be h interrupt control register 14 icr14 w, r/w 00000111 b 0000bf h interrupt control register 15 icr15 w, r/w 00000111 b 0000c0 h to 0000c9 h reserved 0000ca h external interrupt enable 1 enir1 r/w external interrupt 1 00000000 b 0000cb h external interrupt source 1 eirr1 r/w xxxxxxxx b 0000cc h detection level setting 1 elvr1 r/w 00000000 b 0000cd h 00000000 b 0000ce h external interrupt sour ce select eissr r/w 00000000 b 0000cf h pll/sub clock control register psccr w pll xxxx0000 b
mb90360e series 25 (continued) address register abbrevia- tion access resource name initial value 0000d0 h to 0000ff h reserved 007900 h to 007917 h reserved 007918 h reload register lc prllc r/w 16-bit ppg c/d xxxxxxxx b 007919 h reload register hc prlhc r/w xxxxxxxx b 00791a h reload register ld prlld r/w xxxxxxxx b 00791b h reload register hd prlhd r/w xxxxxxxx b 00791c h reload register le prlle r/w 16-bit ppg e/f xxxxxxxx b 00791d h reload register he prlhe r/w xxxxxxxx b 00791e h reload register lf prllf r/w xxxxxxxx b 00791f h reload register hf prlhf r/w xxxxxxxx b 007920 h input capture 0 ipcp0 r input capture 0/1 xxxxxxxx b 007921 h input capture 0 ipcp0 r xxxxxxxx b 007922 h input capture 1 ipcp1 r xxxxxxxx b 007923 h input capture 1 ipcp1 r xxxxxxxx b 007924 h input capture 2 ipcp2 r input capture 2/3 xxxxxxxx b 007925 h input capture 2 ipcp2 r xxxxxxxx b 007926 h input capture 3 ipcp3 r xxxxxxxx b 007927 h input capture 3 ipcp3 r xxxxxxxx b 007928 h to 00793f h reserved 007940 h timer data 0 tcdt0 r/w i/o timer 0 00000000 b 007941 h timer data 0 tcdt0 r/w 00000000 b 007942 h timer control status 0 tccsl0 r/w 00000000 b 007943 h timer control status 0 tccsh0 r/w 0xxxxxxx b 007944 h to 00794b h reserved 00794c h timer 2/reload 2 tmr2/ tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx b 00794d h r/w xxxxxxxx b 00794e h timer 3/reload 3 tmr3/ tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx b 00794f h r/w xxxxxxxx b 007950 h to 00795f h reserved
mb90360e series 26 (continued) address register abbrevia- tion access resource name initial value 007960 h clock supervisor control register csvcr r, r/w clock supervisor 00011100 b 007961 h to 00796d h reserved 00796e h can direct mode register (mb90v340e only) cdmr r/w can clock sync xxxxxxx0 b 00796f h to 0079df h reserved 0079e0 h detect address setting 0 padr0 r/w address match detection 0 xxxxxxxx b 0079e1 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e2 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e3 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e4 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e5 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e6 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e7 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e8 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e9 h to 0079ef h reserved 0079f0 h detect address setting 3 padr3 r/w address match detection 1 xxxxxxxx b 0079f1 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f2 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f3 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f4 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f5 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f6 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f7 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f8 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f9 h to 007bff h reserved 007c00 h to 007cff h reserved for can interface 1. refer to ? can controllers? 007d00 h to 007dff h reserved for can interface 1. refer to ? can controllers?
mb90360e series 27 (continued) notes : ? initial value of ?x? represents unknown value. ? any write access to reserved addresses in i/o map s hould not be performed. a read access to reserved addresses results in reading ?x?. address register abbrevia- tion access resource name initial value 007e00 h to 007fff h reserved
mb90360e series 28 can controllers conforms to can specification ver 2.0 part a and part b ? supports transmission/reception in standa rd frame and extended frame formats supports transmitting of data fram es by receiving remote frames 16 transmitting/receiving message buffers ? 29-bit id and 8-byte data ? multi-level message buffer configuration provides full-bit comparison, full-b it mask, acceptance register 0/acce ptance register 1 for each message buffer as id acceptance mask ? 2 acceptance mask registers in either stan dard frame format or extended frame formats bit rate programmable from 10 kbps/s to 2 mbps/s (when input clock is at 16 mhz) list of control registers (1) address register abbreviation access initial value can1 000080 h message buffer valid regi ster bvalr r/w 00000000 00000000 b 000081 h 000082 h transmit request register treqr r/w 00000000 00000000 b 000083 h 000084 h transmit cancel register tcanr w 00000000 00000000 b 000085 h 000086 h transmission complete register tcr r/w 00000000 00000000 b 000087 h 000088 h receive complete regi ster rcr r/w 00000000 00000000 b 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 b 00008b h 00008c h receive overrun register rovrr r/w 00000000 00000000 b 00008d h 00008e h reception interrupt enable register rier r/w 00000000 00000000 b 00008f h
mb90360e series 29 list of control registers (2) address register abbreviation access initial value can1 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 00xxx000 b 007d01 h 007d02 h last event indicator register leir r/w 000x0000 xxxxxxxx b 007d03 h 007d04 h receive and transmit error counter rtec r 00000000 00000000 b 007d05 h 007d06 h bit timing register btr r/w 11111111 x1111111 b 007d07 h 007d08 h ide register ider r/w xxxxxxxx xxxxxxxx b 007d09 h 007d0a h transmit rtr register trtrr r/w 00000000 00000000 b 007d0b h 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 007d0d h 007d0e h transmit interrupt enable register tier r/w 00000000 00000000 b 007d0f h 007d10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx b 007d11 h 007d12 h xxxxxxxx xxxxxxxx b 007d13 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 007d15 h 007d16 h xxxxxxxx xxxxxxxx b 007d17 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 007d19 h 007d1a h xxxxxxxx xxxxxxxx b 007d1b h
mb90360e series 30 list of message buffers (id registers) (continued) address register abbreviation access initial value can1 007c00 h to 007c1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 007c20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 007c21 h 007c22 h xxxxxxxx xxxxxxxx b 007c23 h 007c24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 007c25 h 007c26 h xxxxxxxx xxxxxxxx b 007c27 h 007c28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 007c29 h 007c2a h xxxxxxxx xxxxxxxx b 007c2b h 007c2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 007c2d h 007c2e h xxxxxxxx xxxxxxxx b 007c2f h 007c30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 007c31 h 007c32 h xxxxxxxx xxxxxxxx b 007c33 h 007c34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 007c35 h 007c36 h xxxxxxxx xxxxxxxx b 007c37 h 007c38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 007c39 h 007c3a h xxxxxxxx xxxxxxxx b 007c3b h 007c3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 007c3d h 007c3e h xxxxxxxx xxxxxxxx b 007c3f h
mb90360e series 31 (continued) address register abbreviation access initial value can1 007c40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 007c41 h 007c42 h xxxxxxxx xxxxxxxx b 007c43 h 007c44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 007c45 h 007c46 h xxxxxxxx xxxxxxxx b 007c47 h 007c48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 007c49 h 007c4a h xxxxxxxx xxxxxxxx b 007c4b h 007c4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 007c4d h 007c4e h xxxxxxxx xxxxxxxx b 007c4f h 007c50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 007c51 h 007c52 h xxxxxxxx xxxxxxxx b 007c53 h 007c54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 007c55 h 007c56 h xxxxxxxx xxxxxxxx b 007c57 h 007c58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 007c59 h 007c5a h xxxxxxxx xxxxxxxx b 007c5b h 007c5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 007c5d h 007c5e h xxxxxxxx xxxxxxxx b 007c5f h
mb90360e series 32 list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value can1 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx b 007c61 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx b 007c63 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx b 007c65 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx b 007c67 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx b 007c69 h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx b 007c6b h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx b 007c6d h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx b 007c6f h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx b 007c71 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx b 007c73 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx b 007c75 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx b 007c77 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx b 007c79 h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx b 007c7b h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx b 007c7d h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx b 007c7f h
mb90360e series 33 (continued) address register abbreviation access initial value can1 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b
mb90360e series 34 (continued) address register abbreviation access initial value can1 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90360e series 35 interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os corresponding interrupt vector interrupt control register number address number address reset n #08 ffffdc h ?? int9 instruction n #09 ffffd8 h ?? exception n #10 ffffd4 h ?? reserved n #11 ffffd0 h icr00 0000b0 h reserved n #12 ffffcc h can 1 reception n #13 ffffc8 h icr01 0000b1 h can 1 transmission/node status n #14 ffffc4 h reserved n #15 ffffc0 h icr02 0000b2 h reserved n #16 ffffbc h reserved n #17 ffffb8 h icr03 0000b3 h reserved n #18 ffffb4 h 16-bit reload timer 2 y1 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 #20 ffffac h reserved n #21 ffffa8 h icr05 0000b5 h reserved n #22 ffffa4 h ppg c/d n #23 ffffa0 h icr06 0000b6 h ppg e/f n #24 ffff9c h timebase timer n #25 ffff98 h icr07 0000b7 h external interrupt 8 to 11 y1 #26 ffff94 h watch timer n #27 ffff90 h icr08 0000b8 h external interrupt 12 to 15 y1 #28 ffff8c h a/d converter y1 #29 ffff88 h icr09 0000b9 h i/o timer 0 n #30 ffff84 h reserved n #31 ffff80 h icr10 0000ba h reserved n #32 ffff7c h input capture 0 to 3 y1 #33 ffff78 h icr11 0000bb h reserved n #34 ffff74 h uart 0 reception y2 #35 ffff70 h icr12 0000bc h uart 0 transmission y1 #36 ffff6c h uart 1 reception y2 #37 ffff68 h icr13 0000bd h uart 1 transmission y1 #38 ffff64 h
mb90360e series 36 (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : ? the peripheral resources sharing the icr register have the same interrupt level. ? when the peripheral resources sharing the icr regist er use extended intelligent i/o service, only one can use extended intelligent i/o service at a time. ? when either of the 2 peripheral resources sharing the icr register specifies extended intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os corresponding interrupt vector interrupt control register number address number address reserved n #39 ffff60 h icr14 0000be h reserved n #40 ffff5c h flash memory n #41 ffff58 h icr15 0000bf h delayed interrupt generation module n #42 ffff54 h
mb90360e series 37 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avr v ss ? 0.3 v ss + 6.0 v av cc avr* 2 input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current |i clamp | ? 40 ma *6 ?l? level maximum output current i ol1 ? 15 ma *4 i ol2 ? 40 ma *5 ?l? level average output current i olav1 ? 4ma*4 i olav2 ? 30 ma *5 ?l? level maximum overall output current i ol1 ? 125 ma *4 i ol2 ? 160 ma *5 ?l? level average overall output current i olav1 ? 40 ma *4 + 105 c < t a + 125 c i olav2 *5 + 105 c < t a + 125 c i olav1 ? 40 ma *4 ? 40 c t a + 105 c i olav2 *5 ? 40 c t a + 105 c ?h? level maximum output current i oh1 ?? 15 ma *4 i oh2 ?? 40 ma *5 ?h? level average output current i ohav1 ?? 4ma*4 i ohav2 ?? 30 ma *5 ?h? level maximum overall output current i oh1 ?? 125 ma *4 i oh2 ?? 160 ma *5 ?h? level average overall output current i ohav1 ?? 40 ma *4 + 105 c < t a + 125 c i ohav2 *5 + 105 c < t a + 125 c i ohav1 ?? 40 ma *4 ? 40 c t a + 105 c i ohav2 *5 ? 40 c t a + 105 c power consumption p d ? 300 mw operating temperature t a ? 40 + 105 c ? 40 + 125 c*7 storage temperature t stg ? 55 + 150 c
mb90360e series 38 (continued) *1 : this parameter is based on v ss = av ss = 0 v. *2 : set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3 : v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : applicable to pins : p24 to p27, p40 to p44, p50 to p57, p60 to p67, p80, p82 to p87 *5 : applicable to pins : p20 to p23 *6 : applicable to pins : p20 to p27, p40 to p44, p50 to p57, p60 to p67, p80, p82 to p87 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied a co nnecting limit resistance between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is inputted when the micr ocontroller power supply is off (n ot fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltag e may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? recommended circuit sample : *7 : if used exceeding t a = + 105 c, please consult with us due to the restricted reliability. it is ensured to write/erase data to the flash memory between t a = ? 40 c and + 105 c. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90360e series 39 2. recommended conditions (v ss = av ss = 0 v) * : if used exceeding t a = + 105 c, please consult with us due to the restricted reliability. it is ensured to write/erase data to the flash memory between t a = ? 40 c and + 105 c. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation when not using the a/d converter and not flash programming. 3.0 ? 5.5 v maintains ram data in stop mode smoothing capacitor c s 0.1 ? 1.0 f use a ceramic capacitor or com- parable capacitor of the ac char- acteristics. bypass capacitor at the v cc pin should be greater than this capacitor. operating temperature t a ? 40 ?+ 105 c ? 40 ?+ 125 c* c c s ? c pin connection diagram
mb90360e series 40 3. dc characteristics (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max input ?h? voltage v ihs ?? 0.8 v cc ? v cc + 0.3 v pin inputs if cmos hysteresis input levels are selected (except p82, p85) v iha ?? 0.8 v cc ? v cc + 0.3 v pin inputs if automotive input levels are selected v ihs ?? 0.7 v cc ? v cc + 0.3 v p82, p85 inputs if cmos input levels are selected v ihr ?? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc ? 0.3 ? v cc + 0.3 v md input pin input ?l? voltage v ils ?? v ss ? 0.3 ? 0.2 v cc v pin inputs if cmos hysteresis input levels are selected (except p82, p85) v ila ?? v ss ? 0.3 ? 0.5 v cc v pin inputs if automotive input levels are selected v ils ?? v ss ? 0.3 ? 0.3 v cc v p82, p85 inputs if cmos input levels are selected v ilr ?? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss ? 0.3 ? v ss + 0.3 v md input pin output ?h? voltage v oh other than p20 to p23 v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v v ohi p20 to p23 v cc = 4.5 v, i oh = ? 14.0 ma v cc ? 0.5 ?? v output ?l? voltage v ol other than p20 to p23 v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v v oli p20 to p23 v cc = 4.5 v, i ol = 20.0 ma ?? 0.4 v input leak current i il ? v cc = 5.5 v, v ss < v i < v cc ? 1 ? + 1 a pull-up resistance r up p20 to p27, rst ? 25 50 100 k ?
mb90360e series 41 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max pull-down resistance r down md2 ? 25 50 100 k ? mb90362e, mb90362es, mb90362te, mb90362tes power supply current* i cc v cc v cc = 5.0 v, internal frequency : 24 mhz, at normal operation. ? 35 45 ma v cc = 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 50 60 ma flash memory devices v cc = 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 50 60 ma flash memory devices i ccs v cc = 5.0 v, internal frequency : 24 mhz, at sleep mode. ? 12 20 ma i cts v cc = 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.8 ma devices without t-suffix ? 0.4 1.0 devices with t-suffix i ctspll6 v cc = 5.0 v, internal frequency : 24 mhz, at pll timer mode, external frequency = 4 mhz ? 47ma i ccl v cc = 5.0 v internal frequency : 8 khz, at sub operation, t a = + 25 c stopping clock supervisor ? 40 100 a mb90f362e, mb90f367e, mb90362e, mb90367e operating clock supervisor ? 60 150 mb90f367e, mb90367e stopping clock supervisor ? 90 200 MB90F362TE, mb90f367te, mb90362te, mb90367te operating clock supervisor ? 110 250 mb90f367te, mb90367te i ccls v cc = 5.0 v internal frequency : 8 khz, at sub sleep, t a = + 25 c stopping clock supervisor ? 10 50 a mb90f362e, mb90f367e, mb90362e, mb90367e operating clock supervisor ? 30 100 mb90f367e, mb90367e stopping clock supervisor ? 60 150 MB90F362TE, mb90f367te, mb90362te, mb90367te operating clock supervisor ? 80 200 mb90f367te, mb90367te
mb90360e series 42 (continued) (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : the power supply current is m easured with an external clock. parameter sym- bol pin condition value unit remarks min typ max power supply current* i cct v cc v cc = 5.0 v internal frequency : 8 khz, at watch mode, t a = + 25 c stopping clock supervisor ? 830 a mb90f362e, mb90f367e, mb90362e, mb90367e operating clock supervisor ? 30 70 mb90f367e, mb90367e stopping clock supervisor ? 60 130 MB90F362TE, mb90f367te, mb90362te, mb90367te operating clock supervisor ? 80 170 mb90f367te, mb90367te i cch v cc = 5.0 v, at stop mode, t a = + 25 c ? 525 a devices without t-suffix ? 50 130 a devices with t-suffix input capacity c in other than av cc , av ss , avr, v cc , v ss , c ?? 515pf
mb90360e series 43 4. ac characteristics (1) clock timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz 1/2 when pll stops, when using an oscillation circuit 4 ? 16 mhz pll 1, when using an oscillation circuit 4 ? 12 mhz pll 2, when using an oscillation circuit 4 ? 8mhz pll 3, when using an oscillation circuit 4 ? 6mhz pll 4, when using an oscillation circuit 4 ? 4mhz pll 6, when using an oscillation circuit x0, x1 3 ? 24 mhz 1/2 when pll stops, when using an external clock 4 ? 24 mhz pll 1, when using an external clock 4 ? 12 mhz pll 2, when using an external clock 4 ? 8mhz pll 3, when using an external clock 4 ? 6mhz pll 4, when using an external clock 4 ? 4mhz pll 6, when using an external clock f cl x0a, x1a ? 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0, x1 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p whl , p wll x0a 5 15.2 ? s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock f cpl ?? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock t cpl ? 20 122.1 ? s when using sub clock
mb90360e series 44 x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll ? clock timing
mb90360e series 45 guaranteed operation range of mb90360e series * : when using the oscillation circuit, the maximum oscillation clock frequency is 16 mhz. 5.5 3.5 4 1.5 24 4.0 guaranteed operation range guaranteed pll operation range guaranteed a/d converter operation range internal clock f cp (mhz) power supply voltage v cc (v) ? guaranteed pll operation range 24 16 12 8 4.0 1.5 3 4 8 24 12 1/2 16 g ua r a nteed o s cill a tion fre qu ency r a nge extern a l clock f c (mhz) * intern a l clock f cp (mhz) (pll off) 6 4 3 2 1
mb90360e series 46 (2) reset standby input (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : oscillation time of oscillator is the time that the amplitude reaches 90 % . in the crystal oscillator, the oscillation time is between several ms and tens of ms. in cerami c oscillators, the oscillation time is between hundreds of s and several ms. with an external clock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* + 100 s ? ns in stop mode, sub clock mode, sub sleep mode, and watch mode 100 ? s in timebase timer mode rst x0 t rstl 0.2 v cc 0.2 v cc 100 s 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset rst 0.2 v cc t rstl 0.2 v cc ? under normal operation : ? in stop mode, sub clock mode, sub sleep mode, and watch mode :
mb90360e series 47 (3) power-on reset (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) note : if you change the power supply voltage too rapidly, a power-on reset may occur. we recommend that you start up smoothly by restraining voltages when changing the power supp ly voltage during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3 v holds ram data we recommend a rise of 50 mv/ms maximum.
mb90360e series 48 (4) uart0/uart1 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0 v) notes : ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. ? t cp is internal operating clock cycle time (mac hine clock) . refer to ? (1) clock timing?. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0, sck1 internal shift clock mode output pins : c l = 80 pf + 1 ttl. 8 t cp ? ns sck sot delay time t slov sck0, sck1, sot0, sot1 ? 80 + 80 ns valid sin sck t ivsh sck0, sck1, sin0, sin1 100 ? ns sck valid sin hold time t shix sck0, sck1, sin0, sin1 60 ? ns serial clock ?h? pulse width t shsl sck0, sck1 external shift clock mode output pins : c l = 80 pf + 1 ttl. 4 t cp ? ns serial clock ?l? pulse width t slsh sck0, sck1 4 t cp ? ns sck sot delay time t slov sck0, sck1, sot0, sot1 ? 150 ns valid sin sck t ivsh sck0, sck1, sin0, sin1 60 ? ns sck valid sin hold time t shix sck0, sck1, sin0, sin1 60 ? ns sck sot sin v il v ih v il v ih 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v t ivsh t shix t scyc t slov ? internal shift clock mode
mb90360e series 49 (5) trigger input timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0 v) note : t cp is internal operating clock cycle time (mac hine clock) . refer to ? (1) clock timing?. parameter symbol pin condition value unit min max input pulse width t trgh t trgl int8, int9r int10, int11 int12r, int13 int14r, int15r adtg ? 5 t cp ? ns sck v ih t slsh v il sot 0.8 v 2.4 v t slov sin v il v ih t ivsh v il v ih t shix v ih v il t shsl ? external shift clock mode v il v ih t trgh v il v ih t trgl int8, int9r int10, int11 int12r, int13 int14r, int15r adtg
mb90360e series 50 (6) timer related resource input timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0 v) note : t cp is internal operating clock cycle time (mac hine clock) . refer to ? (1) clock timing?. (7) timer related resource output timing (t a = ?40 c to +125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0 v) parameter symbol pin condition value unit min max input pulse width t tiwh tin2, tin3 in0 to in3 ? 4 t cp ? ns t tiwl parameter symbol pin condition value unit min max clk t out change time t to tot2, tot3 ppgc to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin2, tin3 in0 to in3 clk 2.4 v 0.8 v 2.4 v t to tot2, tot3 ppgc to ppgf
mb90360e series 51 5. a/d converter (t a = ? 40 c to + 125 c, 3.0 v avr ? av ss , v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : if a/d converter is not operating, a current when cpu is stopped is applicable (v cc = av cc = avr = 5.0 v) . parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero reading voltage v ot an0 to an15 av ss ? 1.5 av ss + 0.5 av ss + 2.5 v full scale reading voltage v fst an0 to an15 avr ? 3.5 avr ? 1.5 avr + 0.5 v compare time ?? 1.0 ? 16500 s 4.5 v av cc 5.5 v 2.0 4.0 v av cc < 4.5 v sampling time ?? 0.5 ? s 4.5 v av cc 5.5 v 1.2 4.0 v av cc < 4.5 v analog port input current i ain an0 to an15 ? 0.3 ? +0.3 a analog input voltage range v ain an0 to an15 av ss ? avr v reference voltage range ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 a* reference voltage supply current i r avr ? 600 900 a i rh avr ?? 5 a* offset between input channels ? an0 to an15 ?? 4lsb
mb90360e series 52 ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting a/ d conversion precision. therefore, to satisfy the a/d conversion precisi on standard, consider the relationship between the external impedance and mi nimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that t he sampling time is longer than the minimum value. and, if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. r c ? analog input equivalent circuit model analog input during sampling : on comparator mb90f362e/te/es/tes, mb90f367e/te/es/tes mb90362e/te/es/tes, mb90367e/te/es/tes, mb90v340e-101/102/103/104 rc 4.5 v av cc 5.5 v 2.0 k ? (max) 16.0 pf (max) 4.0 v av cc < 4.5 v 8.2 k ? (max) 16.0 pf (max) rc 4.5 v av cc 5.5 v 2.0 k ? (max) 14.4 pf (max) 4.0 v av cc < 4.5 v 8.2 k ? (max) 14.4 pf (max) note : the values are reference values.
mb90360e series 53 ? about errors as | avr ? av ss | becomes smaller, values of relative errors grow larger. ? at 4.5 v av cc 5.5 v minimum sampling time [ s] (external impedance = 0 k ? to 20 k ? ) ? at 4.0 v av cc < 4.5 v (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) ? the relationship between external impedance and minimum sampling time external impedance [k ? ] (external impedance = 0 k ? to 100 k ? ) mb90362e/te/es/tes, mb90367e/te/es/tes, mb90 v 340e-101/102/103/104 mb90f362e/te/es/tes mb90f367e/te/es/tes 100 90 8 0 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 20 1 8 16 14 12 10 8 6 4 2 0 01234567 8 mb90362e/te/es/tes, mb90367e/te/es/tes, mb90 v 340e-101/102/103/104 mb90f362e/te/es/tes mb90f367e/te/es/tes minimum sampling time [ s] external impedance [k ? ] 100 90 8 0 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 mb90362e/te/es/tes, mb90367e/te/es/tes, mb90 v 340e-101/102/103/104 mb90f362e/te/es/tes mb90f367e/te/es/tes 20 1 8 16 14 12 10 8 6 4 2 0 01234567 8 mb90362e/te/es/tes, mb90367e/te/es/tes, mb90 v 340e-101/102/103/104 mb90f362e/te/es/tes mb90f367e/te/es/tes minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ]
mb90360e series 54 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line ( ?00 0000 0000 b ? ?00 0000 0001 b ? ) and full-scale transition line ( ?11 1111 1110 b ? ?11 1111 1111 b ? ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an theoretical value. a total error includes zero transi- tion error, full-scale transition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output ?n? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) = avr ? av ss 1024 [v] v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] v nt : a voltage at which digital output transits from (n ? 1) to n. n : a/d converter digital output value
mb90360e series 55 (continued) 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h av ss avr av ss avr n + 1 h n h n ? 1 h n ? 2 h v ot ( a ct ua l me asu rement v a l u e ) { 1 l s b (n ? 1) + v ot } act ua l conver s ion ch a r a cteri s tic s v f s t ( a ct ua l me asu rement v a l u e) v nt ( a ct ua l me asu rement v a l u e) act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s digit a l o u tp u t digit a l o u tp u t an a log inp u t an a log inp u t v nt ( a ct ua l me asu rement v a l u e) v (n + 1) t ( a ct ua l me asu rement v a l u e) non linearity error differential linearity error non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = n : a/d converter digital output value v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .?
mb90360e series 56 7. flash memory program/erase characteristics * : corresponding value comes from the technology reliability evaluation result (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter conditions value unit remarks min typ max chip erase time t a = ? 40 c to + 105 c v cc = 5.0 v ? 115s excludes programming prior to erasure word (16-bit width) programming time ? 16 3600 s except for the overhead time of the system level program/erase cycle ? 10000 ?? cycle flash memory data retention time average t a = + 85 c 20 ?? year *
mb90360e series 57 ordering information part number package remarks mb90f362epmt 48-pin plastic lqfp (fpt-48p-m26) MB90F362TEpmt mb90f362espmt MB90F362TEspmt mb90f367epmt mb90f367tepmt mb90f367espmt mb90f367tespmt mb90362epmt mb90362tepmt mb90362espmt mb90362tespmt mb90367epmt mb90367tepmt mb90367espmt mb90367tespmt mb90v340e-101 299-pin ceramic pga (pga-299c-a01) for evaluation mb90v340e-102 mb90v340e-103 mb90v340e-104
mb90360e series 58 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 4 8 -pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 7 7 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.17 g code (reference) p-lfqfp4 8 -7 7-0.50 4 8 -pin pl as tic lqfp (fpt-4 8 p-m26) (fpt-4 8 p-m26) c 200 3 fujit s u limited f4 8 040 s -c-2-2 24 1 3 3 625 4 8 3 7 index s q 9.000.20(. 3 54.00 8 ) s q 0.1450.055 (.006.002) 0.0 8 (.00 3 ) "a" 0?~ 8 ? .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0.600.15 (.024.006) 0.100.10 (.004.004) ( s t a nd off) 0.25(.010) det a il s of "a" p a rt 1 12 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) lead no. (mo u nting height) .276 ?.004 +.016 ?0.10 +0.40 7.00 * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90360e series 59 main changes in this edition the vertical lines marked in the left side of the p age show the changes. page section change results ?? added the following part numbers. (mb90367e(s)/te(s), mb90f367e(s)/te(s), mb90v340e-103/104) 1 description added a description of the "clock supervisor". 2 features added a description of the "clock supervisor". 26 i/o map added the "clock supervisor control register". 41 electrical characteristics 3. dc characteristics added the ratings for the "clock supervisor" to the "i ccl " section of the power supply current ratings. added the ratings for the "clock supervisor" to the "i ccls " section of the power supply current ratings. 42 added the ratings for the "clock supervisor" to the "i cct " section of the power supply current ratings.
mb90360e series f0701 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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